Die interconnection scheme for providing a high yielding process for high performance microprocessors

ABSTRACT

A method is disclosed. The method includes a plurality of semiconductor sections and an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die. The interconnection structure includes one or more bridge die to connect one or more of the plurality of semiconductor sections to one or more other semiconductor sections or a top layer interconnect structure that connects the plurality of semiconductor sections or both the one or more bridge die and the top layer interconnect structure.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.16/236,228, filed on Dec. 28, 2018, the entire contents of which ishereby incorporated by reference herein.

TECHNICAL FIELD

Embodiments of the disclosure pertain to providing a high yieldingprocess for high performance microprocessors and, in particular, to adie interconnection scheme for providing a high yielding process forhigh performance microprocessors.

BACKGROUND

Fabricating high performance microprocessors in a low yielding processpresents significant challenges to chip designers. High performancemicroprocessor architectures can include very high numbers ofinterconnected compute and network elements. The larger the contiguoussilicon area, the greater the challenge (exponentially so) of yielding afully functional die. The large size of the network part of highperformance microprocessor architectures result in large total die area.Consequently, large size network elements are difficult to yield,especially in a relatively low yielding manufacturing process.

Rapid product lifecycles and high development costs pressuremanufacturing firms to cut not only their development times(time-to-market), but also the time to reach full capacity utilization(time-to-volume). The period between completion of development and fullcapacity utilization is known as production ramp-up. During that time,new production processes are not well understood, and contributes to lowyields and low production rates. However, because of the aforementionedpressures some yield is required during early ramp-up and debug phases.Conventional approaches to addressing yield and performance in highperformance microprocessor development rely upon packaging techniques orembedded bridges. These approaches come with large power and performancepenalties. Accordingly, many useful high performance microprocessorarchitecture designs cannot be built using current approaches.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustration of an example graphics, server, fieldprogrammable gate array (FPGA), artificial intelligence (AI), system onchip (SOC) or other large architecture.

FIG. 2A illustrates the manner in which a large architecture can beseparated into computation and interconnect components according to aprevious approach.

FIG. 2B illustrates the manner in which a base die can be separated intoa first base die section and a second base die section.

FIG. 2C illustrates the manner in which a first base die section and asecond base die section can be connected by a bridge die.

FIG. 2D illustrates another manner in which a first base die section anda second base die section can be connected by a bridge die.

FIGS. 3A-3C illustrate the formation of a top layer interconnectionstructure used to connect base die sections to form a functionallymonolithic base die according to an embodiment.

FIGS. 4A-4C illustrate the manner in which bridge die can be used toconnect base die sections to form a functionally monolithic base dieaccording to an embodiment.

FIGS. 5A-5C illustrate a situation where a top layer interconnectionstructure is used and a situation where bridge die are used to connectbase die sections according to an embodiment.

FIG. 6A illustrates a wafer that includes a plurality of die accordingto an embodiment.

FIG. 6B is a flowchart of a die harvesting process according to anembodiment.

FIG. 6C illustrates die quadrants associated with a reticle according toan embodiment.

FIG. 7 shows a flowchart of a method for providing high performancemicroprocessor die according to an embodiment.

FIG. 8 illustrates a computing device in accordance with oneimplementation of an embodiment.

FIG. 9 illustrates an interposer that includes one or moreimplementations of an embodiment.

DESCRIPTION OF THE EMBODIMENTS

A die interconnection scheme for providing a high yielding process forhigh performance microprocessors is described. It should be appreciatedthat although embodiments are described herein with reference to exampledie interconnection schemes for providing a high yielding process forhigh performance microprocessors, the disclosure is more generallyapplicable to die interconnection schemes for providing a high yieldingprocess for high performance microprocessors as well as other type dieinterconnection schemes for providing a high yielding process for highperformance microprocessors. In the following description, numerousspecific details are set forth, such as specific integration andmaterial regimes, in order to provide a thorough understanding ofembodiments of the present disclosure. It will be apparent to oneskilled in the art that embodiments of the present disclosure may bepracticed without these specific details. In other instances, well-knownfeatures, such as integrated circuit design layouts, are not describedin detail in order to not unnecessarily obscure embodiments of thepresent disclosure. Furthermore, it is to be appreciated that thevarious embodiments shown in the Figures are illustrativerepresentations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description forthe purpose of reference only, and thus are not intended to be limiting.For example, terms such as “upper”, “lower”, “above”, and “below” referto directions in the drawings to which reference is made. Terms such as“front”, “back”, “rear”, and “side” describe the orientation and/orlocation of portions of the component within a consistent but arbitraryframe of reference which is made clear by reference to the text and theassociated drawings describing the component under discussion. Suchterminology may include the words specifically mentioned above,derivatives thereof, and words of similar import.

Rapid product lifecycles and high development costs pressuremanufacturing firms to cut not only their development times(time-to-market), but also the time to reach full capacity utilization(time-to-volume). The period between completion of development and fullcapacity utilization is known as production ramp-up. During that time,new production processes are not well understood, and contributes to lowyields and low production rates. However, because of the aforementionedpressures some yield is required during early ramp-up and debug phases.Conventional approaches to addressing yield and performance in highperformance microprocessor development rely upon packaging techniques orembedded bridges. These approaches come with large power and performancepenalties. Moreover, their large die requirements can impose prohibitivelimits on yield and die size. Accordingly, many useful high performancemicroprocessor architecture designs cannot be built using currentapproaches.

An approach that addresses the shortcomings of previous approaches isdisclosed herein. For example, as part of a disclosed process, a highperformance microprocessor design is broken into parts. In particular,the compute portion of the design is broken into parts and placed onsmaller high performance die and the network portion of the design isbroken into parts and placed on respective base die sections. During thefabrication of the base die, stitch wires are used to connectinterconnect structures of the severable base die sections onto whichthe parts of the network circuitry are placed such that a functionallymonolithic base die can be formed from the base die sections. In anembodiment, the blocks of the network circuitry that are unique areabstracted out and placed on small chiplets. These chiplets can beconnected to die by micro-bumps (formed from conductive material). In anembodiment, the chiplets can be used as redundant bridge die to connectindividual base die sections taken from different parts of a wafer suchthat a functionally monolithic base die can be constructed from suchindividual base die sections. During the low yield phase of productionramp up, the bridge die are used to provide a base die constructed inwhole, or in part, from individual base die sections that provides alevel of performance that is desired by some customers. During the highyield phase of production ramp up, the bridge chips do not have to beused and the stitch wires may be used to provide a base die formed froma single semiconductor block that provides 10 times higher bandwidthbetween the dies than is provided by conventional bridge die. As aresult, in an embodiment, during early production ramp up and debug ofparts, one or more bridge die can be used to construct a version of thedesign that enables the provision of required yield. Moreover, duringhigh volume production ramp up, interconnect stitching can be used toprovide a higher performance version of the design. Thus, valuablemicroprocessor architectures can be built that cannot be built usingconventional techniques because of the prohibitive limits imposed onyield and die size by their large base die requirement. Embodiments areapplicable to graphics, server, Artificial Intelligence (AI), FieldProgrammable gate array (FPGA) logic, System on Chip (SOC) and othermicroprocessor architectures.

FIG. 1 is an illustration of a conventional microprocessor architecture100. The microprocessor architecture 100 shown in FIG. 1 is typical ofgraphics or server architectures. In the FIG. 1 example, themicroprocessor architecture 100 includes computation elements 101,interconnect (e.g., network) elements 103 and interconnect wires 105.Referring to FIG. 1 the interconnect elements 103 are connected to aplurality of other interconnect elements 103 and to individualcomputation elements 101 by interconnect wires 105. The computationelements 101 can be formed using the latest generation processtechnology (N) and the interconnect elements 103 can be formed using aprevious generation process technology (N−1).

It should be appreciated that because the microprocessor architecture100 is very large, attempts to fabricate the microprocessor architecture100 using conventional approaches can result in a low yieldingproduction process. In order to increase yield, the design can beseparated into parts in order to effect a higher yielding productionprocess. Because the fabrication of the computation elements 101 caninvolve a lower yielding production process than does the fabrication ofthe interconnect elements 103, the design can be separated alongcomputation and interconnect component lines. For example, thecomputation elements 101 and the interconnect elements 103 can befabricated on separate die. However, because the interconnection portionof the microprocessor architecture 100 is itself very large, and thefabrication of such as a monolithic structure can result in a lowyielding production process, the interconnect elements 101 of themicroprocessor architecture 100 can themselves can be fabricated onindividual die.

FIG. 2A illustrates the manner in which a microprocessor architecturesuch as that shown in FIG. 1 can be separated into computation andinterconnect components according to a previous approach. FIG. 2A showsa wafer 200 and a cross-section of a portion of the wafer 200 thatincludes a plurality of computation die that include computationcomponents of the large microprocessor architecture mounted on a basedie that includes interconnect components of the large microprocessorarchitecture thereon according to a previous approach. The cross-sectionof the portion of the wafer 200 shown in FIG. 2A includes base die 201,first computation die 203 a, second computation die 203 b, bumps 205 aand 205 b, interconnect network 207, bumps 209, vias 211, active devicelayer 213, conductive layers 215, active device layer 217 a, activedevice layer 217 b, conductive layer 219 a and conductive layer 219 b.

Referring to FIG. 2A, the base die 201 is formed underneath the firstcomputation die 203 a and second computation die 203 b. The bumps 205 aand 205 b are formed on the base die 201 and connect the base die 201 tothe first computation die 203 a and the second computation die 203 brespectively. The interconnect network 207 is formed as a part of theconductive layers 215 and includes interconnect elements and isconnected to computation elements. The bumps 209 are formed below thebase die 201 and enable the base die 201 to be connected to externalcircuitry (e.g., circuitry of a package substrate). The vias 211 areformed in the base die 201. In an embodiment, the vias 211 are verticalinterconnection structures that facilitate electrical interconnection.The active device layer 213 is formed on the base die 201 and includesactive devices (as does other active device layers 217 a and 217 b). Theconductive layers 215 are formed on the active device layer 213. In anembodiment, the conductive layers 215 facilitate electrical connectionto external connection components (as does other conductive layers 219 aand 219 b). The active device layer 217 a is formed on the firstcomputation die 203 a. The active device layer 217 b is formed on thesecond computation die 203 b. The conductive layer 219 a is formed onthe active device layer 217 a. The conductive layer 219 b is formed onthe active device layer 217 b.

Thus, FIG. 2A illustrates a manner in which the networking andcomputation components of a large microprocessor architecture can beseparated where its interconnect (networking) components are formed onthe base die 201 and its computation components are formed on thecomputation die 203 a and 203 b. However, because the networkingcomponents of the base die 201 can be very large, the base die 201 mayneed to be separated such that the resulting die sections can beaccommodated by a reticle in a manner that addresses yield and costconsiderations. FIG. 2B illustrates a manner in which the base die 201of FIG. 2A, can be separated into a first base die section 201 a and asecond base die section 201 b. In FIG. 2B, the first base die section201 a includes bumps 209 a and vias 211 a and the second base diesection 201 b includes bumps 209 b and vias 211 b. These and othercomponents of FIG. 2B function similarly to their counterparts in FIG.2A and thus a description of their function is not repeated here forpurposes of clarity and brevity. The separation of the die into aplurality of smaller sections produces die of reduced size that arepatterned using masks that can fit into reticles of standard size suchthat yield and cost considerations are addressed.

FIG. 2C shows a manner in which the first base die section 201 a and thesecond base die section 201 b can be connected by a bridge die 221 in aprevious approach. Referring to FIG. 2C, in a first example, the bridgedie 221 is formed in a package substrate 223. Furthermore, the firstbase die section 201 a and the second base die section 201 b are formedon the package substrate 223 and are connected by the bridge die 221.FIG. 2D shows another manner in which the first base die section 201 aand the second base die section 201 b can be connected by the bridge die221 in a previous approach. FIG. 2D shows in addition to commonstructures shown in FIG. 2C, active layer 213 a, active layer 213 b,conductive layers 215 a and conductive layers 215 b. These and othercomponents of FIG. 2D function similarly to their counterparts in FIG.2C and thus a description of their function is not repeated here forpurposes of clarity and brevity. Referring to FIG. 2D, the bridge die221 is connected to bumps above a top surface of the first base diesection 201 a and above a top surface of the second base die section 201b and forms a bridge that communicatively couples the first base diesection 201 a and the second base die section 201 b. It should beappreciated that the bridge die connection approaches illustrated inFIGS. 2C and 2D provide a ten times lower bandwidth than monolithic diearchitectures. In addition, these approaches can involve die wastage onthe base die due to the addition of mesh or interconnect input andoutput circuitry which can increase the cost of the base die.

In contrast to the approaches described hereinabove, in an embodiment, adie structure is provided that is in a first phase of production ramp updesigned to use bridge die to connect individual base die sections thatare identified as functional to one or more other base die sectionsidentified as functional in order to provide a functionally monolithicbase die, and is in a second phase of production ramp up designed to usean interconnect structure to connect severable but intact base diesections together when adjacent base die sections are identified asfunctional. In an embodiment, because of the aforementioned diearchitecture, functionally monolithic base dies can be provided duringboth the low yield and the high yield phases of production ramp up,through the use of bridge die and stitched interconnect structures,respectively. The embodiments that include these features are describedin detail with reference to FIGS. 3A-3C, FIGS. 4A-4C and FIGS. 5A-5Cbelow.

FIGS. 3A-3C illustrate the formation of a top layer interconnectionstructure used to connect base die sections to form a functionallymonolithic base die according to an embodiment. FIGS. 4A-4C illustratethe manner in which bridge die connection circuitry can be formed andbridge die can be used to connect individual base die sections to form afunctionally monolithic base die according to an embodiment. FIGS. 5A-5Cillustrate examples in which bridge die can be used to connectindividual base die sections and in which a top layer interconnectionstructure can be used to connect intact base die sections according toan embodiment.

In FIGS. 3A-3C, reticles are shown that are associated with first andsecond sections of a base die and illustrate the manner in whichinterconnect masks of the reticles are connected using a stitch maskaccording to an embodiment. FIG. 3A shows reticle 301, reticle 303 andscribe line 305. Referring to FIG. 3A, the reticle 301 and the reticle303, are used to project interconnect mask patterns onto first andsecond sections of a base die. The scribe line 305 is formed on the diefor use as a guide for a saw or other device that can be used toseparate the sections. In FIG. 3A, reticles associated with a first anda second section of a base die are shown, however, the base die can bedivided into other numbers of sections, corresponding to the number ofsections into which the interconnect circuitry is divided. For example,a base die can be divided into 4, 6 or more sections (in FIGS. 5A-5C amicroprocessor base die that is divided into 4 sections or “quadrants”is described). FIG. 3B shows a top layer interconnects mask 307 and atop layer interconnects mask 309 associated respectively with reticle301 and reticle 303. In an embodiment, the top layer interconnects mask307 and the top layer interconnects mask 309 are used to project a maskpattern onto a first base die section associated with reticle 301 and asecond base die section associated with reticle 303. The mask patternthat is formed on the first base die section and the mask pattern thatis formed on the second base die section are used to form top layerinterconnects on the first base die section and top layer interconnectson the second base die section. In an embodiment, a space is leftbetween the top layer interconnects on the first base die section andthe top layer interconnects formed on the second base die section.However, in an embodiment, the top layer interconnects mask 307 and thetop layer interconnects mask 309 can be connected by a stitch wires maskthat is formed in the space. FIG. 3C shows such a stitch wires mask 311that can be used to bridge the space between the top layer interconnectsmask 307 and the top layer interconnects mask 309. In an embodiment, thestitch wires mask 311 is used in the projection of a stitch wirespattern onto a first base die section associated with the reticle 301and a second base die section associated with the reticle 303 betweenthe top layer interconnects on the first base die section and the toplayer interconnects on the second base die section. The stitch wirespatterns are used to form conductors on the first base die section andconductors on the second base die section that connects the top layerinterconnects on the first base die section and the top layerinterconnects on the second base die section. In FIG. 3C, the scribeline 305 shown as surrounding the reticle 301 and the reticle 303,circumscribes the patterns used to form the interconnections and thestitch mask on the first and the second sections of a base die. In anembodiment, when the interconnections and stitch wires connect thesections of a base die a functionally monolithic base die can be formedfrom those sections of the base die.

As shown in FIG. 3B and FIG. 3C, in an embodiment, the interconnectionsfor respective sections of the base die can be formed from a uniformreticle. Moreover, in an embodiment, the mask patterns in the reticlesassociated with the sections of the base die can be the same. In otherembodiments, the mask patterns associated with the sections of the basedie can be different. In an embodiment, in contrast to previousapproaches, the mesh or interconnect logic is not formed on suchsections of the base die. In an embodiment, the mesh or interconnectlogic is provided by bridge die. This approach addresses base diewastage and excessive cost. In an embodiment, this multi-purpose bridgedie can either be implemented as active embedded bridges or as mounted“on die” interconnects as is discussed herein with reference to FIGS.4A-4C.

FIG. 4A shows the areas of first and second reticles from which the maskpatterns for connection circuitry for bridge die are transferred tofirst and second base die sections according to an embodiment. In FIG.4A the first and second reticles correspond to first and second base diesections and include mask patterns for connection circuitry for bridgedie that are transferred to the first and second base die sectionsaccording to an embodiment. FIG. 4A shows reticle A 401, reticle B 403,scribe line 405, connection circuitry mask for bridge die 401 a-401 dand connection circuitry mask for bridge die 403 a-403 d.

Referring to FIG. 4A, the connection circuitry mask for bridge die 401a-401 d and the connection circuitry mask for bridge die 403 a-403 d areformed around the periphery of the reticle A 401 and the reticle B 403respectively. In FIG. 4A, the connection circuitry masks for bridge die401 a and 403 c are used to form connection circuitry for connecting abridge die that connects a first and a second base die section. In anembodiment, the bridge die can be used in the low yield phase of theproduction ramp-up process to improve yield. In an embodiment, thebridge die used in this manner can improve yield by providingconnectivity between base die sections that have been identified asfunctional. The identified base die sections can be connected using thebridge die to provide a functionally monolithic base die. In anembodiment, the bridge die includes the unique functional blocks of thetop layer interconnects. In an embodiment, as compared to the bridge diethat are shown in FIGS. 2C and 2D the unique functional blocks areeliminated from the top layer interconnects and are provided as a partof the bridge die. For example, in an embodiment, the bridge die caninclude interconnect or mesh logic that is not provided as part of thetop layer interconnects that are formed as part of base die sections. Inan embodiment, the bridge die can be either provided as active embeddedbridges or as “on die” interconnection bridges. In an embodiment, whenthe bridge die are either provided as active embedded bridges or as “ondie” interconnection bridges, the bridge die can be connected tocircuitry in the die sections to which it is coupled that is designed tosupport die-to-die connection.

FIGS. 4B and 4C show package assemblies that include a multi-purposebridge die that is used to connect a first base die section and a secondbase die section. The package assemblies shown in FIGS. 4B and 4Cinclude components that are similar to those of the package assembliesshown in FIGS. 2C and 2D and thus a detailed description of suchcomponents are not made again here for purposes of clarity and brevity.For example, FIG. 4B shows base die section 421 a, base die section 421b, first computation die 423 a, second computation die 423 b, bumps 425a and 425 b, interconnect network 427, bumps 429 a and 429 b, packagesubstrate 431, vias 435 a and 435 b, active device layer 437, conductivelayers 439, active device layers 441 a and 441 b, and conductive layers443 a and 443 b. Moreover, FIG. 4C shows in addition to commonstructures shown in FIG. 4B, active layer 437 a, active layer 437 b,conductive layers 439 a and conductive layers 439 b. FIGS. 4B and 4Cshow in addition to the components that are shown in FIGS. 2C and 2D,multi-purpose bridge die 433. FIGS. 4B and 4C illustrate embedded and ondie bridge die configurations of multi-purpose bridge die 433respectively.

Referring to FIGS. 4B and 4C, the multi-purpose bridge die 433 connectsthe first base die section 421 a and the second base die section 421 b.In an embodiment, in addition to interconnect conductors, themulti-purpose bridge die 433 can include interconnect or mesh logic. Forexample, in an embodiment, multi-purpose bridge die 433 can includerouting logic and/or other types of logic. In an embodiment, themulti-purpose bridge die 433 can include an SRAM structure thatincorporates interconnect layers. In an embodiment, the multi-purposebridge die 433 can include filtering circuitry. For example, themulti-purpose bridge die 433 can include circuitry that can cachetraffic for reuse. In an embodiment, the multi-purpose bridge die 433can be formed from a plurality of semiconductor layers. For example, inan embodiment, the multi-purpose bridge die 433 can be formed from one,two, three, four or more semiconductor layers. In other embodiments, themulti-purpose bridge die 433 can be formed from other numbers ofsemiconductor layers. In an embodiment, the multi-purpose bridge die 433can be formed from one, two, three, four or more SRAM layers. In otherembodiments, the multi-purpose bridge die 433 can include other numbersof SRAM layers. In an embodiment, the multi-purpose bridge die 433 canbe formed from silicon. In other embodiments, the multi-purpose bridgedie 433 can be formed from other semiconductor material.

In an embodiment, the connections formed on the base die sections by themasks can be used in conjunction with the multi-purpose bridge die 433.In an embodiment, using the interconnections formed using theinterconnections masks and the stitch mask in conjunction with one ormore multi-purpose bridge die 433 can provide a functionally monolithicbase die with greater performance capabilities than can be provided by abase die that includes base die sections only connected byinterconnections formed using the interconnection masks and the stitchmask or by base die connected by bridge die alone.

FIG. 5A illustrates sectional lines along which a base die can bedesigned to be severable or separable to form individual base diesections and the sectional lines along which individual base diesections can be connected by multi-purpose bridge die according to anembodiment. FIG. 5A shows base die quadrants 501-507 and input/output(I/O) components 509 a-509 d. It should be appreciated that in anembodiment, the base die quadrants 501-507 are designed to beconnectable by multi-purpose bridge die to components in addition toother base die quadrants such as the input/output (I/O) components 509a-509 d shown in FIG. 5A. In FIG. 5A, the base die is divided intoquadrants that if found to be defective can be replaced with functionalquadrants. In an embodiment, the functional quadrants can be from thesame wafer. In an embodiment, the functional quadrants can be found in afunctional quadrant identification process. Referring to FIG. 5A, whenyield is low, such as when the functional die on a wafer fall below agiven threshold, functional quadrants can be identified and connectedwith one or more multi-purpose bridge die in order to form a completedbase die structure. In this manner, a base die structure that isfunctionally monolithic can be provided from multi-purpose bridge dieconnected base die quadrants. In an embodiment, the threshold can be adefect density threshold. In an embodiment, one or more of the base diequadrants 501-507 can be connected using one or more multi-purposebridge die. For example, in an embodiment, a single one of the base diequadrants may be connected to other functional base die quadrants usingmulti-purpose bridge die, and, in other embodiments, more than a singleone of the base die quadrants can be connected to one or more otherfunctional base die quadrants using one or more multi-purpose bridgedie. FIG. 5B illustrates the manner in which base die quadrants thathave been identified as functional can be organized to form a completedbase structure. Referring to FIG. 5B, a set of base die quadrants arepositioned such that die components located at the interfaces betweenthe base die quadrants are brought into alignment. Thereafter, themulti-purpose bridge die can be positioned to connect the base diequadrants at these interfaces. In FIG. 5B, the thick border shown assurrounding the depicted set of base die quadrants, indicates that thebase die quadrants are connectable to form a functionally monolithicbase die. In an embodiment, one or more of these base die quadrants canbe connected by multi-purpose bridge die to form the functionallymonolithic base die. In an embodiment, the multi-purpose bridge die canbe used in conjunction with the stitch mask described with reference toFIG. 3C. In an embodiment, using one or more multi-purpose bridge die inconjunction with the stitch mask can provide a functionally monolithicbase die with greater performance capabilities than can be provided by abase die that includes base die quadrants only connected with a stitchmask or only connected by multi-purpose bridge die. In an embodiment, anindividual base die quadrant can be added or removed to increase ordecrease the level of performance that is provided. In this manner, theperformance of a microprocessor can be calibrated to meet the needs ofparticular markets as is desired. For example, in an embodiment,performance can be calibrated to suit the needs of markets for thehighest performance, less high performance and least high performanceversions of a microprocessor that includes the base die. FIG. 5C shows amonolithic base die that includes four severable but intact base diequadrants identified as functional. In an embodiment, a stitch mask suchas that described with reference to FIG. 3C can be used to connect thefour base quadrants of the monolithic base die that are identified asfunctional. In an embodiment, such a monolithic base die structure ismost likely to be identified in the high yield phase of production rampup. Referring to FIG. 5C, in an embodiment, when such a base die isidentified, it can be singulated intact with a stitch wires in placethat provide die-to-die connection.

In an embodiment, based on the identification of defects in die on awafer, designers can determine actions that include but are not limitedto how the die are harvested, how the die are cut, how the die areconnected, and the manner in which functions can be de-featured.

FIG. 6A shows a wafer 600 that includes a plurality of die. Theplurality of die includes die that are a part of full reticle diequadrants (a set of die quadrants that contain a microprocessor) inaddition to individual die quadrants that are positioned around fullreticles according to an embodiment. In the FIG. 6A embodiment, a fullreticle includes four die quadrants. In other embodiments, a fullreticle can include other numbers of die sections. FIG. 6A shows fullreticle die quadrants 601 and individual die quadrants 603.

Referring to FIG. 6A, full reticle die quadrants that include, in anembodiment, four die quadrants, are formed in the central part of thewafer 600. The individual die quadrants 603 are formed around the edgeof the wafer 600 where a full reticle cannot fit. In an embodiment,forming individual die quadrants around the edge of the wafer 600 canincrease the number of die quadrants provided by the wafer 600 by tenpercent. In other embodiments, forming individual die quadrants aroundthe edge of the wafer 600 in this manner can increase the number of diequadrants provided by the wafer 600 by other amounts. In an embodiment,all known good die can be extracted from the wafer 600 such that diewastage is eliminated or reduced.

In an embodiment, an example base die reticle can include 4×220 mm²sized quadrants. In other embodiments, base die reticles having othersizes can be used. In an embodiment, the die on a wafer can be flippedand inverted. FIG. 6B is a flowchart of a die harvesting processaccording to an embodiment. Referring to FIG. 6B, the process includes,at 621, forming stitching structures to connect top layer interconnectscorresponding to die quadrants of sets of die quadrants to providedie-to-die connection without a bridge on a wafer. In an embodiment, thestitching structures can be formed in a layer above the top layerinterconnects. In other embodiments, the stitching structures can beformed in other manners. At 623, singulating the wafer into sets of diequadrants and testing the sets of die quadrants. In an embodiment thewafer is singulated into 2×2 macro-dice. In other embodiments, the wafercan be singulated into macro-dice having other structures. At 625,determining if the quadrants pass sort. If all quadrants of a set of diequadrants pass sort, at 627, harvesting the set of die quadrants on asingle semiconductor base. In an embodiment, the set of die quadrantscan be harvested as a 1× (1 part) macro base where the basesemiconductor is left intact. In an embodiment, in this case the socketis built for a single semiconductor base die for best performance. In anembodiment, the socket can be built for a single silicon base die. Ifall four quadrants do not pass sort, at 629, performing a second passsingulation and leaving one or more functional quadrants of the set ofdie quadrants. In an embodiment, a socket can be built to accommodate a4× (4 part) base die in order to maximize yield. For 220 mm² base die,an extra 10% of quadrants can be fit into space around the edge of thewafer where a full reticle does not fit. In other embodiments, othersized die can be fit into space around the edge of the wafer where afull reticle does not fit. FIG. 6C show die quadrants 641-647 associatedwith a reticle. Referring to FIG. 6C, one of the quadrant die 641 hasbeen identified as being bad (non-functional, defective, etc.) in aprocess such as that described with reference to FIG. 6B. The otherthree dies of the four dies 643-647 are identified as being good(functional, not defective etc.). In an embodiment, the three good diecan be packaged and marketed as a lower performance product for buyerswho do not desire the higher performance versions of the microprocessor.In another embodiment, a functional die can be identified from the waferand connected by one or more bridge die to one or more of the dies643-647 and be packaged and marketed as a product.

FIG. 7 shows a flowchart of a method for providing a die architecturehigh yield and performance microprocessors. Referring to FIG. 7 , themethod includes at 701, forming a plurality of separable semiconductorsections. At 703, forming an interconnection structure that connects theplurality of separable semiconductor sections to provide a functionallymonolithic base die. In an embodiment, the forming the interconnectionstructure includes, forming one or more bridge die to connect one ormore of the plurality of separable semiconductor sections to one or moreother of the plurality of separable semiconductor sections, or forming atop layer interconnect structure to connect the plurality of separablesemiconductor sections or forming both the one or more bridge die andthe top layer interconnect structure.

Implementations of embodiments of the invention may be formed or carriedout on a substrate, such as a semiconductor substrate. In oneimplementation, the semiconductor substrate may be a crystallinesubstrate formed using a bulk silicon or a silicon-on-insulatorsubstructure. In other implementations, the semiconductor substrate maybe formed using alternate materials, which may or may not be combinedwith silicon, that include but are not limited to germanium, indiumantimonide, lead telluride, indium arsenide, indium phosphide, galliumarsenide, indium gallium arsenide, gallium antimonide, or othercombinations of group III-V or group IV materials. Although a fewexamples of materials from which the substrate may be formed aredescribed here, any material that may serve as a foundation upon which asemiconductor device may be built falls within the spirit and scope ofthe present invention.

A plurality of transistors, such as metal-oxide-semiconductorfield-effect transistors (MOSFET or simply MOS transistors), may befabricated on the substrate. In various implementations of theinvention, the MOS transistors may be planar transistors, nonplanartransistors, or a combination of both. Nonplanar transistors includeFinFET transistors such as double-gate transistors and tri-gatetransistors, and wrap-around or all-around gate transistors such asnanoribbon and nanowire transistors. Although the implementationsdescribed herein may illustrate only planar transistors, it should benoted that the invention may also be carried out using nonplanartransistors.

Each MOS transistor includes a gate stack formed of at least two layers,a gate dielectric layer and a gate electrode layer. The gate dielectriclayer may include one layer or a stack of layers. The one or more layersmay include silicon oxide, silicon dioxide (SiO₂) and/or a high-kdielectric material. The high-k dielectric material may include elementssuch as hafnium, silicon, oxygen, titanium, tantalum, lanthanum,aluminum, zirconium, barium, strontium, yttrium, lead, scandium,niobium, and zinc. Examples of high-k materials that may be used in thegate dielectric layer include, but are not limited to, hafnium oxide,hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide,zirconium oxide, zirconium silicon oxide, tantalum oxide, titaniumoxide, barium strontium titanium oxide, barium titanium oxide, strontiumtitanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalumoxide, and lead zinc niobate. In some embodiments, an annealing processmay be carried out on the gate dielectric layer to improve its qualitywhen a high-k material is used.

The gate electrode layer is formed on the gate dielectric layer and mayconsist of at least one P-type workfunction metal or N-type workfunctionmetal, depending on whether the transistor is to be a PMOS or an NMOStransistor. In some implementations, the gate electrode layer mayconsist of a stack of two or more metal layers, where one or more metallayers are workfunction metal layers and at least one metal layer is afill metal layer.

For a PMOS transistor, metals that may be used for the gate electrodeinclude, but are not limited to, ruthenium, palladium, platinum, cobalt,nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-typemetal layer will enable the formation of a PMOS gate electrode with aworkfunction that is between about 4.9 eV and about 5.2 eV. For an NMOStransistor, metals that may be used for the gate electrode include, butare not limited to, hafnium, zirconium, titanium, tantalum, aluminum,alloys of these metals, and carbides of these metals such as hafniumcarbide, zirconium carbide, titanium carbide, tantalum carbide, andaluminum carbide. An N-type metal layer will enable the formation of anNMOS gate electrode with a workfunction that is between about 3.9 eV andabout 4.2 eV.

In some implementations, the gate electrode may consist of a “U”-shapedstructure that includes a bottom portion substantially parallel to thesurface of the substrate and two sidewall portions that aresubstantially perpendicular to the top surface of the substrate. Inanother implementation, at least one of the metal layers that form thegate electrode may simply be a planar layer that is substantiallyparallel to the top surface of the substrate and does not includesidewall portions substantially perpendicular to the top surface of thesubstrate. In further implementations of the invention, the gateelectrode may consist of a combination of U-shaped structures andplanar, non-U-shaped structures. For example, the gate electrode mayconsist of one or more U-shaped metal layers formed atop one or moreplanar, non-U-shaped layers.

In some implementations of the invention, a pair of sidewall spacers maybe formed on opposing sides of the gate stack that bracket the gatestack. The sidewall spacers may be formed from a material such assilicon nitride, silicon oxide, silicon carbide, silicon nitride dopedwith carbon, and silicon oxynitride. Processes for forming sidewallspacers are well known in the art and generally include deposition andetching process steps. In an alternate implementation, a plurality ofspacer pairs may be used, for instance, two pairs, three pairs, or fourpairs of sidewall spacers may be formed on opposing sides of the gatestack.

As is well known in the art, source and drain regions are formed withinthe substrate adjacent to the gate stack of each MOS transistor. Thesource and drain regions are generally formed using either animplantation/diffusion process or an etching/deposition process. In theformer process, dopants such as boron, aluminum, antimony, phosphorous,or arsenic may be ion-implanted into the substrate to form the sourceand drain regions. An annealing process that activates the dopants andcauses them to diffuse further into the substrate typically follows theion implantation process. In the latter process, the substrate may firstbe etched to form recesses at the locations of the source and drainregions. An epitaxial deposition process may then be carried out to fillthe recesses with material that is used to fabricate the source anddrain regions. In some implementations, the source and drain regions maybe fabricated using a silicon alloy such as silicon germanium or siliconcarbide. In some implementations the epitaxially deposited silicon alloymay be doped in situ with dopants such as boron, arsenic, orphosphorous. In further embodiments, the source and drain regions may beformed using one or more alternate semiconductor materials such asgermanium or a group III-V material or alloy. And in furtherembodiments, one or more layers of metal and/or metal alloys may be usedto form the source and drain regions.

One or more interlayer dielectrics (ILD) are deposited over the MOStransistors. The ILD layers may be formed using dielectric materialsknown for their applicability in integrated circuit structures, such aslow-k dielectric materials. Examples of dielectric materials that may beused include, but are not limited to, silicon dioxide (SiO2), carbondoped oxide (CDO), silicon nitride, organic polymers such asperfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass(FSG), and organosilicates such as silsesquioxane, siloxane, ororganosilicate glass. The ILD layers may include pores or air gaps tofurther reduce their dielectric constant.

FIG. 8 illustrates a computing device 800 in accordance with oneimplementation of the invention. The computing device 800 houses a board802. The board 802 may include a number of components, including but notlimited to a processor 804 and at least one communication chip 806. Theprocessor 804 is physically and electrically coupled to the board 802.In some implementations the at least one communication chip 806 is alsophysically and electrically coupled to the board 802. In furtherimplementations, the communication chip 806 is part of the processor804.

Depending on its applications, computing device 800 may include othercomponents that may or may not be physically and electrically coupled tothe board 802. These other components include, but are not limited to,volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flashmemory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, atouchscreen controller, a battery, an audio codec, a video codec, apower amplifier, a global positioning system (GPS) device, a compass, anaccelerometer, a gyroscope, a speaker, a camera, and a mass storagedevice (such as hard disk drive, compact disk (CD), digital versatiledisk (DVD), and so forth).

The communication chip 806 enables wireless communications for thetransfer of data to and from the computing device 800. The term“wireless” and its derivatives may be used to describe circuits,devices, systems, methods, techniques, communications channels, etc.,that may communicate data through the use of modulated electromagneticradiation through a non-solid medium. The term does not imply that theassociated devices do not contain any wires, although in someembodiments they might not. The communication chip 806 may implement anyof a number of wireless standards or protocols, including but notlimited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE,GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well asany other wireless protocols that are designated as 3G, 4G, 5G, andbeyond. The computing device 800 may include a plurality ofcommunication chips 806. For instance, a first communication chip 806may be dedicated to shorter range wireless communications such as Wi-Fiand Bluetooth and a second communication chip 806 may be dedicated tolonger range wireless communications such as GPS, EDGE, GPRS, CDMA,WiMAX, LTE, Ev-DO, and others.

The processor 804 of the computing device 800 includes an integratedcircuit die packaged within the processor 804. In some implementationsof the invention, the integrated circuit die of the processor includesone or more devices, such as MOS-FET transistors built in accordancewith implementations of the invention. The term “processor” may refer toany device or portion of a device that processes electronic data fromregisters and/or memory to transform that electronic data into otherelectronic data that may be stored in registers and/or memory.

The communication chip 806 also includes an integrated circuit diepackaged within the communication chip 806. In accordance with anotherimplementation of the invention, the integrated circuit die of thecommunication chip includes one or more devices, such as MOS-FETtransistors built in accordance with implementations of the invention.

In further implementations, another component housed within thecomputing device 800 may contain an integrated circuit die that includesone or more devices, such as MOS-FET transistors built in accordancewith implementations of the invention.

In various implementations, the computing device 800 may be a laptop, anetbook, a notebook, an ultrabook, a smartphone, a tablet, a personaldigital assistant (PDA), an ultra mobile PC, a mobile phone, a desktopcomputer, a server, a printer, a scanner, a monitor, a set-top box, anentertainment control unit, a digital camera, a portable music player,or a digital video recorder. In further implementations, the computingdevice 800 may be any other electronic device that processes data.

FIG. 9 illustrates an interposer 900 that includes one or moreembodiments of the invention. The interposer 900 is an interveningsubstrate used to bridge a first substrate 902 to a second substrate904. The first substrate 902 may be, for instance, an integrated circuitdie. The second substrate 904 may be, for instance, a memory module, acomputer motherboard, or another integrated circuit die. Generally, thepurpose of an interposer 900 is to spread a connection to a wider pitchor to reroute a connection to a different connection. For example, aninterposer 900 may couple an integrated circuit die to a ball grid array(BGA) 906 that can subsequently be coupled to the second substrate 904.In some embodiments, the first and second substrates 902/904 areattached to opposing sides of the interposer 900. In other embodiments,the first and second substrates 902/904 are attached to the same side ofthe interposer 900. And in further embodiments, three or more substratesare interconnected by way of the interposer 900.

The interposer 900 may be formed of an epoxy resin, afiberglass-reinforced epoxy resin, a ceramic material, or a polymermaterial such as polyimide. In further implementations, the interposermay be formed of alternate rigid or flexible materials that may includethe same materials described above for use in a semiconductor substrate,such as silicon, germanium, and other group III-V and group IVmaterials.

The interposer may include metal interconnects 908 and vias 910,including but not limited to through-silicon vias (TSVs) 912. Theinterposer 900 may further include embedded devices 914, including bothpassive and active devices. Such devices include, but are not limitedto, capacitors, decoupling capacitors, resistors, inductors, fuses,diodes, transformers, sensors, and electrostatic discharge (ESD)devices. More complex devices such as radio-frequency (RF) devices,power amplifiers, power management devices, antennas, arrays, sensors,and MEMS devices may also be formed on the interposer 900. In accordancewith embodiments of the invention, apparatuses or processes disclosedherein may be used in the fabrication of interposer 900.

Example embodiment 1: A die including a plurality of semiconductorsections, an interconnection structure connecting the plurality ofsemiconductor sections to provide a functionally monolithic base die,the interconnection structure includes: one or more bridge die thatconnect one or more of the plurality of semiconductor sections to one ormore other semiconductor sections, or a top layer interconnect structurethat connects the plurality of semiconductor sections or both the one ormore bridge die and the top layer interconnect structure.

Example embodiment 2: The die of example embodiment 1, wherein the toplayer interconnect structure includes stitch wires that connect toplayer interconnects that correspond to a first semiconductor section totop layer interconnects that correspond to a second semiconductorsection.

Example embodiment 3: The die of example embodiment 1, wherein thebridge die is connected above first and second semiconductor sections.

Example embodiment 4: The die of example embodiment 1, wherein thebridge die is connected underneath first and second semiconductorsections.

Example embodiment 5: The die of example embodiment 1, wherein thebridge die includes interconnect input/output (I/O) logic.

Example embodiment 6: The die of example embodiment 1, wherein thebridge die includes a plurality of SRAM semiconductor layers.

Example embodiment 7: The die of example embodiment 1, 2, 3, 4, 5 or 6wherein the plurality of semiconductor sections includes separablequadrants.

Example embodiment 8: A package includes a package substrate and a dieincluding: a plurality of semiconductor sections, an interconnectionstructure connecting the plurality of semiconductor sections to providea functionally monolithic base die, the interconnection structureincludes: one or more bridge die that connect one or more of theplurality of semiconductor sections to one or more other semiconductorsections or a top layer interconnect structure that connects theplurality of semiconductor sections or both the one or more bridge dieand the top layer interconnect structure. The package also includes acomputation die above each of the semiconductor sections.

Example embodiment 9: The package of example embodiment 8, wherein thetop layer interconnect structure includes stitch wires that connect toplayer interconnects that correspond to a first semiconductor section totop layer interconnects that correspond to a second semiconductorsection.

Example embodiment 10: The package of example embodiment 8, wherein thebridge die is connected above first and second semiconductor sections.

Example embodiment 11: The package of example embodiment 8, wherein thebridge die is connected underneath first and second semiconductorsections.

Example embodiment 12: The package of example embodiment 8, wherein thebridge die includes interconnect input/output (I/O) logic.

Example embodiment 13: The package of example embodiment 8, wherein thebridge die includes a plurality of SRAM semiconductor layers.

Example embodiment 14: The package of example embodiment 8, 9, 10, 11,12 or 13 wherein the plurality of semiconductor sections includesseparable quadrants.

Example embodiment 15: A method, comprising forming stitching structuresto connect interconnects corresponding to die quadrants of sets of diequadrants on a wafer, singulating the wafer into the sets of diequadrants and testing the sets of die quadrants, determining if all ofthe quadrants of the sets of die quadrants pass testing, if all of thequadrants of a set of die quadrants pass testing, harvesting the set ofdie quadrants on a single semiconductor base, and if all of thequadrants of the set of die quadrants do not pass testing, performing asecond singulation and leaving one or more functional die quadrants ofthe set of die quadrants.

Example embodiment 16: The method of example embodiment 15, furthercomprising: forming one or more bridge die to connect the one or morefunctional die quadrants to one or more other functional die quadrants.

Example embodiment 17: The method of example embodiment 15, wherein theforming the stitching structures include forming stitch wires thatconnect top layer interconnects that correspond to a first die quadrantto top layer interconnects that correspond to a second die quadrant.

Example embodiment 18: The method of example embodiment 16, wherein theforming the one or more bridge die includes connecting the bridge dieabove the one or more functional die quadrants and the one or more otherfunctional die quadrants.

Example embodiment 19: The method of example embodiment 16, wherein theforming the one or more bridge die includes connecting the bridge dieunderneath the one or more functional die quadrants and the one or moreother functional die quadrants.

Example embodiment 20: The method of example embodiment 15, 16, 17, 18or 19 wherein forming the one or more bridge die includes forming aninterconnect to input/output (I/O) logic.

What is claimed is:
 1. A die, comprising: a plurality of semiconductorsections; and an interconnection structure connecting the plurality ofsemiconductor sections to provide a functionally monolithic base die,wherein the interconnection structure includes a top layer interconnectstructure that is discontinuous between adjacent ones of the pluralityof semiconductor sections, and the interconnection structure includes abridge die, the bridge die on a same side of the plurality ofsemiconductor sections as the top layer interconnect structure.
 2. Thedie of claim 1, wherein the bridge die is attached to the top layerinterconnect structure.
 3. The die of claim 1, wherein the bridge dieincludes interconnect input/output (I/O) logic.
 4. The die of claim 1,wherein the bridge die includes a plurality of SRAM semiconductorlayers.
 5. The die of claim 1, wherein the top layer interconnectstructure includes stitch wires that connect top layer interconnects. 6.The die of claim 1, wherein the plurality of semiconductor sectionsincludes separable quadrants.
 7. A die, comprising: a first base diesection and a second base die section; and an interconnection structureconnecting the first base die section and the second base die section,wherein the interconnection structure includes a top layer interconnectstructure that is discontinuous between the first base die section andthe second base die section, and the interconnection structure includesa bridge die, the bridge die on a same side of the first base diesection and the second base die section as the top layer interconnectstructure.
 8. The die of claim 7, wherein the bridge die is attached tothe top layer interconnect structure.
 9. The die of claim 7, wherein thebridge die includes interconnect input/output (I/O) logic.
 10. The dieof claim 7, wherein the bridge die includes a plurality of SRAMsemiconductor layers.
 11. The die of claim 7, wherein the top layerinterconnect structure includes stitch wires that connect top layerinterconnects.
 12. A package, comprising: a package substrate; a die onthe package substrate including: a plurality of semiconductor sections;and an interconnection structure connecting the plurality ofsemiconductor sections to provide a functionally monolithic base die,wherein the interconnection structure includes a top layer interconnectstructure that is discontinuous between adjacent ones of the pluralityof semiconductor sections, and the interconnection structure includes abridge die, the bridge die on a same side of the plurality ofsemiconductor sections as the top layer interconnect structure; and adie above each of the plurality of semiconductor sections.
 13. Thepackage of claim 12, wherein the bridge die is attached to the top layerinterconnect structure.
 14. The package of claim 12, wherein the bridgedie includes interconnect input/output (I/O) logic.
 15. The package ofclaim 12, wherein the bridge die includes a plurality of SRAMsemiconductor layers.
 16. The package of claim 12, wherein the top layerinterconnect structure includes stitch wires that connect top layerinterconnects.
 17. The package of claim 12, wherein the plurality ofsemiconductor sections includes separable quadrants.